Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore’s Law and the ITRS roadmap created a semi-standardized path forward for the chip industry.
Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have added the flexibility needed to target specific applications, markets, and use cases. Those approaches also have made it easier to integrate various types and amounts of memories and processing elements into a package. And analog sensors and other components that were developed at, or optimized for, an established process node can be integrated with other components developed at new or older nodes. However, all of this flexibility, integration, and specialization comes at a cost: Increased complexity. While some problems are simpler, such as designing a power delivery network or floor-planning for heat or data flow, the integration of multiple chips can cause a wide range of interactions — some of which may only show up in one particular implementation. This is particularly problematic for inspection, metrology, and test, because not all of the pieces of a unique design may be accessible. Unique designs. Because many of these designs are customized for a particular application or market segment, there are few, if any, off-the-shelf models for design, aging, or manufacturing (PDKs). Varied lifetimes. Some of these packages are being developed for automotive, mil/aero, and industrial applications, where lifetimes can be as long as 25 years. Others may only be expected to last a few years. That requires a deep understanding of all the individual parts, as well as the interconnects and the packaging materials, in order to function properly throughout that lifetime. It’s likely that not all of them will age evenly. Unlike in the past, when a design was perfected for 1 billion units, some of these devices are being rolled out in much more limited quantities, and all of this is happening under much tighter time constraints. “Different companies are taking different approaches, whether it’s a fan-in or fan-out,” said Subodh Kulkarni, CEO of CyberOptics. “Within those, there are various different approaches, like TSMC’s CoWoS [chip-on-wafer-on-substrate]. Samsung has its own version. So the classic mantra of the semiconductor industry, where everything is standardized and billions of chips are made the same way, is breaking apart in the advanced packaging world. Every company is charting its own course to some extent.” That will have to change at some point in order to bring these designs into the mainstream and to connect the pieces across the supply chain. “Everyone in the ecosystem now has a say in building a system, and each one has to play their part,” said Kent Stahn, package design engineer at Synopsys. “Standards will be required to achieve high volume and to have a high impact on failure. In addition, we will need time-sensitive data, and that data has to be actionable.” Still, this presents a tricky balance between mass production and customization. Packaging adds flexibility and options for specialization that are not feasible on a planar device, even for those companies with the deepest pockets. Scaling of digital logic already is out of sync with other technologies, such as memory, and analog gains nothing by scaling it to a smaller geometry. In fact, there are so many possible configurations that even finding overlaps between devices to simplify manufacturing and test is difficult at this point. While that could change with the introduction of standard interfaces and chiplets, the current approaches put pressure on equipment makers, foundries, and packaging houses to build flexibility into their products and processes, and it’s not always feasible. Sometimes it requires more or different equipment. And on the design side, it requires complex partitioning, keeping in mind a whole slew of possible physical/proximity effects, often in multiple dimensions — along the x, y, and z axes, as well as over time. “We can create this heterogeneous integration that allows us to put the chips into a system and input completely different kinds of chips, whether it’s analog, mixed signal, digital, or even sensors,” said Yin Chang, senior vice president at ASE, in a recent presentation. “Die partitioning can improve yield, and the ability to integrate high-bandwidth memory and the ability to re-use various IP and reduce the power is key for integration.” Chang said the key is to provide options for the most efficient way to create high-density integrated packages, whether those are used for AI, high-performance data centers, or 5G millimeter wave devices that incorporate antennas into the package. “So there is a tremendous toolbox to allow designers to create the next SiP (system in package) for a specific solution, whether it is on the edge, or a high-density solution that can be used on the server.” Fig. 1: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE Manufacturing challenges Each of those options adds its own challenges. For example, material mismatches can cause stress on a package, which in turn can reduce life expectancy for some essential components. “Chip-package interaction (CPI) has become a critical reliability issue for fab process migration to advanced nodes using copper/low-K, ultra low-K, or extreme low-K dielectric material,” said K.M. Chen, director of UMC’s Test and Package Engineering Service Division. “There is thermo-mechanical deformation and stress development inside the package during assembly, which affects subsequent reliability tests due to the mismatch of the coefficients of thermal expansion between the chip and the substrate. Fabs need to enhance FBEoL (far back end of line) film strength, adhesion, and structure to ensure a robust packaging process window for CPI solutions.” Teams developing these devices need to consider a whole range of possible effects and interactions. “Regarding advanced packaging evolution, copper pillar, FOWLP (fan-out wafer-level packaging), and 2.5D/3D-IC, the fab FBEoL film needs to optimize more film strength, adhesion and structure to integrate different chips and technology nodes,” Chen said. “Importantly, hybrid bonding needs stringent wafer CMP (chemical mechanical polishing) process control and material selection to achieve reliable wafer bonding for wafer-to-wafer or chip-to-wafer.” So while a nanometer-sized particle left over from polishing a wafer may not cause a problem on a planar chip, it can cause a slew of problems when two chips are bonded together. And an impurity in one chip, or in the materials used to bond those chips, can impact the whole multi-chip package, resulting in reduced yield and higher costs. Impurities can creep in from anywhere in the materials supply chain. They can be undetectable particles in a 50-gallon drum filled with high-viscosity material, or they can be nanometer-sized flaws deep in a substrate or interposer. “There is difficulty in balancing product specifications for different demands,” said Tom Brown, executive director of manufacturing, quality and logistics at Brewer Science. “There is a rising cost to produce high-end, ultra-clean, zero-defect materials for the leading-edge semiconductor manufacturers. The continuous improvement to hit those quality levels are difficult to justify in other materials not used in building the critical components of the chip, but which are highly critical to the packaging and stacking of the chips to meet the overall performance requirements. But the environmental conditions and controls are not necessarily at the same criticality level for every product. As a materials provider, knowing where to invest — and being able to capture a return on the investment when chip manufacturers are also trying to drive costs down — becomes an ever-increasing challenge.” The same is true on the packaging side. “There’s a lot of variation from our substrate suppliers, and we’re constantly pushing them for improvement,” said Curtis Zwenger, vice president of R&D at Amkor Technology. “On the assembly side there is a lot of variation with solder paste inspection, with the jetting that we use in case high-precision stencils aren’t adequate. What we’ve learned in SiP is that it can be a highly manual process, so we have a concerted effort to really improve process quality and yield in variation control through automation.” Fig. 2: Cross section of the bottom of an RDL substrate. Source: Amkor Yield and cost calculations need to factor in all of the chips and components in a package, as well as the package itself. A failure rate of 0.001% may be acceptable for a chip, but that needs to be multiplied by the cost of all the chips and interconnects and extra steps in a complex package, including every step of the design, manufacturing and test flows. “Whether you use DUV or EUV, you know the materials that are needed and the requirements that are specified,” said Brown. “But with packaging, there is not yet a standard process or approach, so the material sets are different for each technology being used by the various customers — temporary or permanent; panel or individual; slide, laser, or chemical release. You have to create a significant portfolio of materials used for different purposes, with different equipment sets and vastly different critical design parameters that impact your production process, control, specifications and testing.” Those considerations are essential to ensuring these devices can be manufactured, that they will yield at predictable levels, and that they will function as expected throughout their expected lifetimes. But they also have to apply across a wide variety of packaging architectures. “Different applications have different chip-package interaction qualification requirements,” said UMC’s Chen. “To meet these criteria, process/material/structure optimization is needed in both wafer foundry and packaging OSATs to ensure robust CPI solutions. Different technologies and nodes have different design rule support, and they need to pass full CPI qualification to ensure the design and reliability are able to fulfill the requested requirements.” Test, inspection and metrology challenges Fully understanding which are the best options for a particular application will take years, and even then there will be a flood of new options and developments that will need to be considered. “All this heterogeneous integration has fragmented the marketplace,” said CyberOptics’ Kulkarni. “When you look at the actual architecture, the spread is quite wide. That impacts all the companies that are involved in the packaging industry. The specific processes they’re using are quite different, which means the inspection and metrology needs to be quite different. So when we get called in by any of these large fabs or packaging houses and look at the actual package, even though at high level they may say it’s fan-in or fan-out, the actual packages from different companies look quite different. The gaps are different, the spacings are different, the heights are different. Where we do see commonalities is they are all getting expensive and the parts are getting smaller, and they all want 100% inspection right now — but we are not there today.” The same is true on the test side. “Electrical testing in itself only provides confidence that the chip in its current unstressed state is electrically good,” said Ben Meihack, product marketing specialist at Onto Innovation. “It does not account for stress that will be exerted on the silicon post-bonding or encapsulation. One example of where this could lead to an immediate failure, post-die-attach, is from a latent sidewall crack that did not manifest in a deviation in performance under test. In this scenario, the post-bond process could lead to the crack expansion beyond the crack arrest structure until a free surface is reached, and kill the die and package.” Variation adds another challenge. As with defects and contamination, variation in a package can be additive with multiple chips. “The increasingly complex advanced packaging techniques are requiring tighter process windows for many variation types,” said Chet Lenox, senior director for industry and customer collaboration at KLA. “A classic example would be how variation in micro-bump heights, before thermo-compression bonding, continue to need to be reduced as target micro-bump pitches decrease. But in addition, we are seeing advanced packaging driving entirely new integration schemes in order to meet variation and cleanliness requirements. For example, the use of plasma dicing for very clean, low-particle singulation is growing significantly.” That also drives up equipment costs, because not all equipment can detect problems in the most advanced packages. This is particularly true for 5G, where production volumes are in the hundreds of millions or billions of units. “On the high-end IC substrates used in advanced packaging, the reduced tolerance to current process variation is driving higher levels of inspection, and in more cases the use of automated optical shaping of shorts and opens to increase yield,” Lenox said. “In addition, impedance control to meet 5G RF requirements has clearly translated into increased requirements for CD and 3D metrology.” Materials and stress Advanced packaging requires expertise in mechanical and electrical engineering, materials science, economics, supply chain management, and domain expertise for whatever market application the device is being created. “There are several ways these demands have impacted manufacturing processes,” said Brewer’s Brown. “First, as end user expectations increase, customers’ performance requirements become more extensive. For example, a typical product certificate of acceptance may have once required only 10 items as criteria. Now, some customers have over 200 requirements listed on the COA (certificate of analysis). Additionally, our customers’ production lines are realizing increased sensitivity to minor variations in their products, resulting in a tightening of existing expectations. Specification limits and control limits tighten with each generation.” These concerns are being echoed across the supply chain. “Material engineering for conformal films and thin films is becoming a super-hot topic,” said David Fried, vice president of computational products at Lam Research. “Material engineering is one of the most important aspects in thin film development. Previously, we used material engineering to induce device stress for performance. We’re well past that application these days. But what we’re finding is that every material we deposit has some intrinsic strain to it, and those characteristics have a lot of implications on the device, the integration, and the result.” That has an impact on the ability to detect any aberrations, particularly once multiple chips are packaged together. This is evident test side, where probe cards are becoming both more customized, complex, and numerous for each design. “In a phone, you need to be able to supply a test solution for each part, as well as a solution for when they are integrated together,” said Alan Liao, director of product marketing at FormFactor. “One example is high-bandwidth memory, where you integrate a four- to eight-stack memory vertically, and then integrate that, through a silicon interposer, with an SoC chip next to it. We can test each individual memory chip at the wafer with one touchdown, one shot, to tell you whether the die is good or bad.” But that’s just step one. The memory also needs to be stacked and tested, and the interposer and SoC need to be tested. “The challenging part is the memory is provided by one company, the SoC is provided by a different company, and the packaging house provides the silicon interposer and packages them together,” Liao said. “With only one chip, you can tell whether it’s good or bad and you know if you’re buying a good chip or a bad chip. But if the whole package fails, who takes responsibility? You need that data to be able to work out the business model.” Tradeoffs Whether these multi-chip packages work as expected depends heavily on use cases, and the kinds of tradeoffs made around those use cases. Use cases for this technology can vary greatly, and that determines how these packages actually look, behave, and ultimately yield. “There are two main drivers,” said Mike Kelly, vice president of advanced packaging development and integration at Amkor Technology. “One is for companies that want to get something into the market fast because it’s a new market and they want to test it out. This provides a toehold. The second is, ‘We really need to build something that’s amazing for this market because there are plenty of people here now. So what else can we do?’ Each of those is going to be very different. But the whole packaging arena is absolutely critical for the future of semiconductors because scaling beyond 3nm is scary. The problem is there are so many options that it’s hard to figure out which way to go.” Consider power, for example. “One of the things everybody’s running into in these newer nodes is that the operating voltages are coming down,” Kelly said. “So there’s less margin for error. That means the ICs are operating with less tolerance for any variation. Getting local charge storage close to the die is become even more important. We’re definitely seeing this at 5nm, and we anticipate it’s going to be much worse at 3nm. So now you have smaller margins to handle tolerance. On top of that, there’s mechanical variation, thermal variation and everything else.” Fig. 3: Mechanical failure in RDL. Source: Amkor Packaging can help to cushion some of these effects. But it also adds new ones, such as thermal dissipation, mechanical stress, and uneven aging. Understanding what goes into a package, how everything is connected together, and where it will be used, are vital upfront decisions. “There was a packaging conference a couple years ago and there was a lot of debate about what to do with these complex, heterogeneous packages,” said Keith Schaub, vice president of technology and strategy at Advantest America. “The answer is, ‘It depends.’ Is it something that’s consumer-based and non-critical, so you would just throw it away if it wasn’t working? Or is it a SpaceX or NASA component? Some problems may be easier to solve if you just have duplicate technology, like the kind of redundancy they build into space missions. If a computer fails, you’ve got another one.” Not every application will support that kind of approach, both for cost reasons and form factor limitations. It’s one thing to put redundancy into a satellite. It’s quite another to add that redundancy into a wearable device, such as augmented reality glasses. The latter requires much tighter control of all the possible unknowns. “When you go from a known good die to a known good system, there are manufacturing and design considerations,” said Dennis Ciplickas, vice president of advanced solutions at PDF Solutions. “Just like when you build an SoC, you have a PDK and you need to design and simulate to that PDK. But no PDK is perfect, and you end up having to guard-band or make certain assumptions about what your real operating conditions will be and how that’s modeled during design. And then, when you finally get the chip out, you’re testing it and evaluating it against all of those assumptions. But that process isn’t perfect, either.” With multi-chip packages, that’s even more difficult. “If you look at a module or a system in package, you have the same problem hierarchically,” Ciplickas said. “So every individual chip is a known good die, but is it operating the way I expected under the hood? And am I able to test it and evaluate and prove it’s good for those operating conditions? One of the challenges in SiPs is achieving the performance you would hope to have gotten by building a really big single chip. But it’s much more expensive to integrate all of that into a single chip, and maybe even impossible with analog components. So by definition you’re going to be using complex, high-speed interfaces between these elements. Now, what are your assumptions? What kind of guard-banding are you’re putting in? And how do you actually test that and evaluate the die operating at that speed before you plug them in the chip, and then into the module, and then when you assemble the module?” Lifecycle management challenges These uncertainties have opened the door to new business models around silicon lifecycle management and data analytics. “Advanced packaging adds another layer of complexity because it lacks visibility and relies on a high-density architecture, which limits redundancy fallbacks,” said Gal Carmel, general manager of proteanTecs’ Automotive Division. “In addition, the AI portion of the chips is growing. It’s not only about packaging and advanced nodes, but the fact that the chip architecture is AI-driven and uses in-field inferencing and training to continuously improve the hardware architecture. Using that feedback loop, you can reduce hardware redundancies and optimize complexities.” That’s essential for long-term reliability monitoring. Changing architectures and placement can increase heat or other stress effects, which in term can impact a variety of age-related effects. “Chips in a package do not age at the same rate,” said Woo Young Han, applications engineering manager at Onto. “Some chips age prematurely compared to others in the same package and cause the whole unit to fail prematurely. Semiconductor chips used in automotive devices are exposed to extreme environments (heat and cold), and extreme temperature is adding a lot of stress to these chips. Defects such as hairline cracks on dies may not have any effect at the early stage of chips usage, but extreme temperature can cause these cracks to grow and cause chip failure. This is why 100% visual defect inspection is mandatory for automotive devices.” And even when there is no room for full redundancy, there can be selective redundancy around such components as the interconnects. “With an interposer, you can have redundant TSVs,” said Synopsys’ Stahn. “You can do temperature cycling over the lifetime of the device, which makes it more robust. This can be used on the package substrate, as well. You also can add more sensors into silicon to tell how a device is aging and how soon it will become unreliable. Was it exposed to high temperatures or not? Analytics is a new piece to it, and you can analyze what will happen if it was exposed for a long period of time.” This does add some overhead into the package design, but the tradeoff is preventing system failure. “The use case defines the budget for overhead,” Stahn said. “If it’s a wearable, it may not matter. In a network, cloud, or server environment, you need to figure out how to test and build in that redundancy so it can survive longer.” Those kinds of concerns can crop up anywhere in the supply chain. Cristina Matos, technology director for wafer-level packaging materials at Brewer, noted that some of the materials used in packages are intended to be permanent, while others are sacrificial — burned or polished off during manufacturing. “Permanent materials are subject to harsh conditions and must survive the device’s expected lifetime without any chemical or mechanical changes,” she said. “In order to achieve industry expectations, we have focused on designing new materials and balancing structure-property relationships to ensure materials meet expectations of accelerated aging, temperature cycling and harsh storage conditions.” And finally, if something does fail in the field, it may not happen for years. What do you do when a critical part needs to be replaced, but it’s no longer available because the company that made it either no longer supports it, was acquired, or went out of business? “We’ve seen cases where companies have built thousands of parts, and when they’re done they destroy all the layers because they don’t want people to reverse engineer them,” said Sam Sadri, senior process engineer at QP Technologies (formerly Quik-Pak). “Then, 20 years later, they ask for more. The only way to deal with that is to remove the package, and use old technology to recreate the mechanical footprint, pitch, and electrical characteristics. This approach has been trending down over the past five years, but now it’s coming back up.” Conclusion As with nearly everything related to advanced packaging, longevity will vary by use case, implementation, and the individual components of the devices inside a package. Known good die are simply one piece of the integrated package. Being able to manufacture, test, inspect and monitor these devices throughout their lifetime is critical, but so is understanding what can go wrong and avoiding those mistakes in the future. The chip industry is only just beginning on this journey because device scaling is becoming so difficult and expensive, and the power/performance/area/cost benefits are shrinking at each new node. At some point, standards will become more commonplace, and more predictable ways of putting these devices together will take over. But all of this takes years, lots of data, and lots of experimentation to determine what works best. Related Stories Variation Threat In Advanced Nodes, Packages Grows Complex interactions and tighter tolerances can impact performance, power and life expectancy. Hunting For Open Defects In Advanced Packages No single screening method will show all the possible defects that create opens. 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