Untangling 3D NAND: Tilt, Registration, And Misalignment

The multiple demands of 3D NAND to enable yield and performance increase in difficulty at each generation. First generation devices, at 24-32 layer pairs, pushed process tools to extremes, going quickly from 10:1 to 40:1 aspect ratios for today’s 64-96…

The multiple demands of 3D NAND to enable yield and performance increase in difficulty at each generation. First generation devices, at 24-32 layer pairs, pushed process tools to extremes, going quickly from 10:1 to 40:1 aspect ratios for today’s 64-96 pair single tier devices. The aspect ratios increased as fast as the manufacturing challenges. To continue bit density scaling, processing improved to enable multi bit storage per layer, but still even more layer pairs are needed. With increasing layer pairs, plasma etch becomes exponentially slower.

This was quickly addressed by tier stacking—splitting the massive stack into two tiers—and it will likely increase to three or more tiers in the future. The advantage of a two-tier process is that it reduces the single etch step to a more manageable process, i.e., two 64 pair etches instead of one 128, or two 96 pair instead of one 192. 256 pair, two or three tier devices, are in development now, and 384 or more expected soon. The channel hole control improved in terms of individual profile, but at the cost of increasing device integration challenges, like adding a joint into the middle of the stack. These integration challenges are confounded by combining variation from multiple process steps. There is an increasing need to identify, measure, separate, and control each of these sources of variability. Fig. 1: 3D NAND aspect ratios bring new challenges for manufacturers. First, we need to level set on some language. Every manufacturer has a similar but different process for their hyperscale 3D NAND devices. Every manufacturer also has different phrases and labels for the various geometric factors that describe the channel hole. The channel hole is the core step around which the 3D NAND device is built. The geometry of the structure and the control is critical to both the yield and reliability of a device. The first four generations of 3D NAND settled on key control: individual pair thicknesses, through stack composition, channel hole profile including a detailed critical dimension from the top to the bottom of the structure. Due to the extreme nature of 3D NAND, other process control factors crept in that became significant including global and localized tilting or tipping of the whole channel hole structure. This results from changes in the deposition process as well as the etching process, which causes new yield modes that were insignificant in planar NAND and other devices, like DRAM. The industry is working hard to keep all these sources under control. The next challenge in tier stacking is the alignment of the final hole. The industry uses overlay, registration, alignment, misalignment, mis-registration and similar words to describe the relative placement of the two channel hole stacks. 3D NAND process control metrology needs to provide ways to measure and separate these factors. The top of the tier location is placed relative to the underlayers through a lithography defined process and is normally defined by registration of the top of Deck 1 to a key underlayer structure (which may or may not contain the drive logic also known as the periphery). The bottom of the first deck will have global and local dimensional variation including tilt, where the bottom wanders from the top by up to tens of nanometers, resulting in bit line (channel hole) failures if they don’t land in the right location. Those tolerances have been engineered to be reasonable in most single tier devices with some self-alignment or landing zone. Two tier devices add a series of challenges. The final joint needs to be well aligned between the two to enable proper downstream processing including a robust electrical connection and access for clean and deposition chemistry, including the most critical storage or charge trap layers that enable the 3D NAND memory cell. When the Deck 2 channel holes are patterned, again the top is defined by a lithographic process and can be very well aligned or registered to the underlying pattern, however those structures incur both critical dimension or profile variation as well as tilt of their own. The manufacturers’ challenge is landing these 80-100nm holes, drilled through microns of material, on top of another 80-100nm hole. Some manufacturers have allotted landing zones or chamfers of the Deck 1 structures to improve margins, but overall, it is an incredibly challenging process to get right trillions of times. Fig. 2: Cross section view shows overlay, tilt and registration challenges for channel hole process control. New innovations in optical metrology are enabling measurement and decomposition of the challenge into individual feedback loops to optimize deposition tools, etch tools, and lithography systems, to improve the total dual tier control. As we move forward to next generation devices, with additional tiers, the manufacturing tolerances will improve, and there are also expected innovations in design and control to deal with the complexity of a final structure with an aspect ratio of over 120:1. Kevin Heidrich (all posts) Kevin Heidrich is senior vice president of marketing and corporate development at Onto Innovation. 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